開講・開催通知

Statistical Static Timing Analysis (SSTA) in Today's SoC Design and Verification [2月23日(木) 福岡工業大学]

2017/01/20

【科目種別】電気エネルギー講座Ⅱ(英語科目)

■講 師: Prof. Dr. Thuy T. Le
■ご所属: San Jose State University

■演 題: Statistical Static Timing Analysis (SSTA) in Today's SoC Design and Verification

■日 時: 平成 29年 2月 23日(木)15:00~16:30
■場 所: 福岡工業大学 E棟3階 Cultivation Site R2教室
      http://www.fit.ac.jp/shisetsu/campus/map/index

■主 催: 福岡工業大学 大学院工学研究科
■申込/お問合せ: 福岡工業大学大学院事務室 master[at]fit.ac.jp

■概要
  Process variations are of great concern in today's design and verification of complex SoC with deep submicron technology. These variations significantly affect the gate delays and hence, the operating frequency of the chip. A timing analysis technique that takes these variations into account is the statistical static timing analysis (SSTA). Since SSTA involves the calculations of probability functions of random variables, few approximations still have to be made such as the types of distributions, correlation among parameters, probability max calculations, linear and non-linear functions of the process parameters, etc. This presentation assesses the fundamentals of the SSTA and the computational models involved. The presentation then shows some of today's study and research that are able to trade-off between model accuracy and the computational complexity of the SSTA.

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